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CD54HC573, cd74hc573 octal transparent d-type latches with 3-state outputs scls454a ? february 2001 ? revised april 2003 1 post office box 655303 ? dallas, texas 75265 2-v to 6-v v cc operation wide operating temperature range of ?55 c to 125 c 3-state outputs directly drive bus lines balanced propagation delays and transition times bus driver outputs drive up to 15 ls-ttl loads significant power reduction compared to ls-ttl logic ics description/ordering information the ?hc573 devices are octal transparent d-type latches designed for 2-v to 6-v v cc operation. when the latch-enable (le) input is high, the q outputs follow the data (d) inputs. when le is low, the q outputs are latched at the logic levels of the d inputs. a buffered output-enable (oe ) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. oe does not affect the internal operations of the latches. old data can be retained or new data can be entered while the outputs are in the high-impedance state. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ordering information t a package ? orderable part number top-side marking pdip ? e tube cd74hc573e cd74hc573e 55 cto125 c soic m tube cd74hc573m hc573m ? 55 c to 125 c soic ? m tape and reel cd74hc573m96 hc573m cdip ? f tube CD54HC573f3a CD54HC573f3a ? package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. copyright ? 2003, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. CD54HC573 ...f p ackage cd74hc573 ...e or m p ackage (top view) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe 1d 2d 3d 4d 5d 6d 7d 8d gnd v cc 1q 2q 3q 4q 5q 6q 7q 8q le on products compliant to mil-prf-38535, all parameters are tested unless otherwise noted. on all other products, production processing does not necessarily include testing of all parameters.
CD54HC573, cd74hc573 octal transparent d-type latches with 3-state outputs scls454a ? february 2001 ? revised april 2003 2 post office box 655303 ? dallas, texas 75265 function table (each latch) inputs output oe le d q l h h h l hl l l lx q 0 h x x z logic diagram (positive logic) oe to seven other channels 1 11 2 19 le 1d c1 1d 1q absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v cc ? 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output drain current per output, i o (v o = 0 to v cc ) 35 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output source or sink current per output, i o (v o = 0 to v cc ) 25 ma . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 2): e package 69 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . m package 58 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. the package thermal impedance is calculated in accordance with jesd 51-7.
CD54HC573, cd74hc573 octal transparent d-type latches with 3-state outputs scls454a ? february 2001 ? revised april 2003 3 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 3) t a = 25 c t a = ? 55 c to 125 c t a = ? 40 c to 85 c unit min max min max min max v cc supply voltage 2 6 2 6 2 6 v v cc = 2 v 1.5 1.5 1.5 v ih high-level input voltage v cc = 4.5 v 3.15 3.15 3.15 v v cc = 6 v 4.2 4.2 4.2 v cc = 2 v 0.5 0.5 0.5 v il low-level input voltage v cc = 4.5 v 1.35 1.35 1.35 v v cc = 6 v 1.8 1.8 1.8 v i input voltage 0 v cc 0 v cc 0 v cc v v o output voltage 0 v cc 0 v cc 0 v cc v v cc = 2 v 1000 1000 1000 t t input transition (rise and fall) time v cc = 4.5 v 500 500 500 ns v cc = 6 v 400 400 400 note 3: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc t a = 25 c t a = ? 55 c to 125 c t a = ? 40 c to 85 c unit cc min max min max min max 2 v 1.9 1.9 1.9 i oh = ? 20 a 4.5 v 4.4 4.4 4.4 v oh v i = v ih or v il 6 v 5.9 5.9 5.9 v i oh = ? 6 ma 4.5 v 3.98 3.7 3.84 i oh = ? 7.8 ma 6 v 5.48 5.2 5.34 2 v 0.1 0.1 0.1 i ol = 20 a 4.5 v 0.1 0.1 0.1 v ol v i = v ih or v il 6 v 0.1 0.1 0.1 v i ol = 6 ma 4.5 v 0.26 0.4 0.33 i ol = 7.8 ma 6 v 0.26 0.4 0.33 i i v i = v cc or 0 6 v 0.1 1 1 a i oz v o = v cc or 0 6 v 0.5 10 5 a i cc v i = v cc or 0, i o = 0 6 v 8 160 80 a c i 10 10 10 pf c o 20 20 20 pf
CD54HC573, cd74hc573 octal transparent d-type latches with 3-state outputs scls454a ? february 2001 ? revised april 2003 4 post office box 655303 ? dallas, texas 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see figure 1) v cc t a = 25 c t a = ? 55 c to 125 c t a = ? 40 c to 85 c unit cc min max min max min max 2 v 80 120 100 t w pulse duration, le high 4.5 v 16 24 20 ns 6 v 14 20 17 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see figure 1) parameter from (input) to (output) load capacitance v cc t a = 25 c t a = ? 55 c to 125 c t a = ? 40 c to 85 c unit (input) (output) capacitance cc min max min max min max 2 v 175 265 220 d q c l = 50 pf 4.5 v 35 53 44 t d 6 v 30 45 37 ns t pd 2 v 175 265 220 ns le q c l = 50 pf 4.5 v 35 53 44 6 v 30 45 37 2 v 150 225 190 t en oe q c l = 50 pf 4.5 v 30 45 38 ns 6 v 26 38 33 2 v 150 225 190 t dis oe q c l = 50 pf 4.5 v 30 45 38 ns 6 v 26 38 33 2 v 60 90 75 t t q c l = 50 pf 4.5 v 12 18 15 ns 6 v 10 15 13 operating characteristics, v cc = 5 v, t a = 25 c parameter typ unit c pd power dissipation capacitance 51 pf
CD54HC573, cd74hc573 octal transparent d-type latches with 3-state outputs scls454a ? february 2001 ? revised april 2003 5 post office box 655303 ? dallas, texas 75265 parameter measurement information test point from output under test c l (see note a) v cc s1 s2 load circuit parameter t pzh t pd or t t t dis t en t pzl t phz t plz open closed s1 closed open s2 open closed closed open open open notes: a. c l includes probe and test-fixture capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. phase relationships between waveforms were chosen arbitrarily. all input pulses are supplied by generators having the followi ng characteristics: prr 1 mhz, z o = 50 ? , t r = 6 ns, t f = 6 ns. d. for clock inputs, f max is measured with the input duty cycle at 50%. e. the outputs are measured one at a time with one input transition per measurement. f. t plz and t phz are the same as t dis . g. t pzl and t pzh are the same as t en . h. t plh and t phl are the same as t pd . r l = 1 k ? voltage waveforms setup and hold and input rise and fall times t h t su 50% v cc 50% v cc 50% 10% 10% 90% 90% v cc v cc 0 v 0 v t r t f reference input data input voltage waveforms propagation delay and output transition times 50% v cc 50% v cc 50% 10% 10% 90% 90% v cc v oh v ol 0 v t r t f input in-phase output 50% v cc t plh t phl 50% v cc 50% 10% 10% 90% 90% v oh v ol t r t f t phl t plh out-of-phase output 0 v t w voltage waveforms pulse duration input 50% v cc 50% v cc v cc output control output waveform 1 (see note b) output waveform 2 (see note b) v ol v oh t pzl t pzh t plz t phz v cc 0 v 50% v cc 10% 50% v cc 0 v voltage waveforms output enable and disable times 50% v cc 50% v cc 90% v cc voltage waveforms recovery time 50% v cc v cc 0 v clr input clk 50% v cc v cc t rec 0 v figure 1. load circuit and voltage waveforms
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples CD54HC573f active cdip j 20 1 tbd a42 n / a for pkg type -55 to 125 CD54HC573f CD54HC573f3a active cdip j 20 1 tbd a42 n / a for pkg type -55 to 125 8512801ra CD54HC573f3a cd74hc573e active pdip n 20 20 pb-free (rohs) cu nipdau n / a for pkg type -55 to 125 cd74hc573e cd74hc573ee4 active pdip n 20 20 pb-free (rohs) cu nipdau n / a for pkg type -55 to 125 cd74hc573e cd74hc573m active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc573m cd74hc573m96 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc573m cd74hc573m96g4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc573m cd74hc573mg4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -55 to 125 hc573m (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 11-apr-2013 addendum-page 2 (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of CD54HC573, cd74hc573 : ? catalog: cd74hc573 ? military: CD54HC573 note: qualified version definitions: ? catalog - ti's standard catalog product ? military - qml certified for military and defense applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant cd74hc573m96 soic dw 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) cd74hc573m96 soic dw 20 2000 367.0 367.0 45.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2

www.ti.com package outline c typ 10.63 9.97 2.65 max 18x 1.27 20x 0.51 0.31 2x 11.43 typ 0.33 0.10 0 - 8 0.3 0.1 0.25 gage plane 1.27 0.40 a note 3 13.0 12.6 b 7.6 7.4 4220724/a 05/2016 soic - 2.65 mm max height dw0020a soic notes: 1. all linear dimensions are in millimeters. dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. this dimension does not include interlead flash. interlead flash shall not exceed 0.43 mm per side. 5. reference jedec registration ms-013. 1 20 0.25 c a b 11 10 pin 1 id area note 4 seating plane 0.1 c see detail a detail a typical scale 1.200
www.ti.com example board layout (9.3) 0.07 max all around 0.07 min all around 20x (2) 20x (0.6) 18x (1.27) (r ) typ 0.05 4220724/a 05/2016 soic - 2.65 mm max height dw0020a soic symm symm land pattern example scale:6x 1 10 11 20 notes: (continued) 6. publication ipc-7351 may have alternate designs. 7. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal solder mask opening non solder mask defined solder mask details solder mask opening metal under solder mask solder mask defined
www.ti.com example stencil design (9.3) 18x (1.27) 20x (0.6) 20x (2) 4220724/a 05/2016 soic - 2.65 mm max height dw0020a soic notes: (continued) 8. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 9. board assembly site may have different recommendations for stencil design. symm symm 1 10 11 20 solder paste example based on 0.125 mm thick stencil scale:6x
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